Job Description

Job Description: Mediatek Egypt is seeking a skilled and motivated Digital Design to join our high-performance team focusing on Ser Des and high-speed interface IP development. The successful candidate will be responsible for the architecture, RTL design, and integration of PHY IP blocks, collaborating with cross-functional teams to ensure high-quality and robust IP solutions for cutting-edge SoCs. Key Responsibilities: PHY IP Architecture Planning: Contribute to the architectural design of PHY IPs for high-speed interfaces such as Ethernet Ser Des, USB, PCIe, HDMI, Display Port, MPHY, and CPHY. RTL Design & Coding: Develop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization. Front-end and Back-end Integration: Handle the integration of PHY IPs in both front-end and back-end design flows, ensuring seamless connectivity and function within the SoC. Cross-functional Collaboration: Work closely with MAC design and Design Verification (DV) teams for system-level IP verification. Collaborate with analog design teams for PHY/Ser Des co-simulation and mixed-signal integration.

Main Requirements and Qualifications

Required Qualifications:Bachelor's degree in communication and Electronics Engineering, Computer Engineering Proficiency in RTL design for digital circuits Familiarity with front-end and back-end integration flows, as well as EDA tools. Practical experience in PHY IP development for high-speed interfaces A solid understanding of high-speed interface standards, including Ethernet Ser Des, PCIe, USB, HDMI, DP, MPHY, and CPHY. Knowledge of DSP-based IP design techniques, such as CDR, CTLE, FEC, FIR, and IIR is preferred. Preferred Skills:Strong problem-solving and debugging abilities. Effective teamwork skills. Excellent communication and documentation capabilities.